EMI and EMC in defence electronics and ‘smart’ battlefield design

The importance of electromagnetic protection in military solutions

Defence electronics cannot rely on commercial-grade devices and regulations, as they understandably have to pass highly rigorous military and aerospace standards to ensure durability in contested environments. Electromagnetic compatibility (EMC) and electromagnetic interference (EMI) relate to how devices handle, generate, and transmit electromagnetic energy. EMI is the noise that disrupts devices, and EMC is the device’s ability to operate properly without being impacted by that noise. In defence EMC design, the ability to prevent system malfunctions is critical for mission viability, electronic warfare (EW) resilience, regulatory compliance and procurement. 

This is our fifth post in our defence electronics series. While LoRa and MAVLink address application-layer concerns, and OTA security spans both software and hardware, EMC is the discipline that runs beneath all of it: electromagnetic performance is a consequence of every other design decision made on the board, which is why this post draws on all four that came before it.

Why electromagnetic compatibility is a defining constraint in defence electronics

Modern defence platforms are among the most electromagnetically hostile environments that electronic hardware encounters. A single armoured vehicle or maritime vessel may carry dozens of radio systems, radar arrays, power conversion units, and data networks, all operating simultaneously within metres of each other. Add the deliberate threat from EW systems designed to jam or disrupt, and it becomes clear why defence EMC design is not simply a compliance checkbox at the end of a project: it’s a foundational design discipline that must be addressed from the earliest schematic stage.

The UK defence sector operates under a layered framework of EMC requirements. DEF STAN 59-411 is the primary standard governing electromagnetic compatibility for UK military equipment, setting out both the emissions limits and immunity thresholds that defence hardware must meet. It builds on the underlying principles of BS EN 61000 and the broader IEC framework but applies them to threat environments, platform classifications, and operational scenarios that commercial EMC standards were never designed to address. Procurement executives and programme managers working on the UK Ministry of Defence (UK MOD) contracts should treat DEF STAN 59-411 compliance as a gateway requirement, not an optional enhancement.

Understanding the EMI threat landscape for UK Defence systems

EMI in the defence context arrives from two distinct categories of source: unintentional and intentional. Unintentional EMI is the electromagnetic noise generated as a by-product of normal electrical operation: switching power supplies, motor drives, digital clock signals, and RF transmitters operating on adjacent channels. Intentional EMI is a deliberate weapon: high-power microwave (HPM) systems, jamming transmitters, directed energy devices, and the broader spectrum of electronic warfare equipment that adversaries deploy specifically to degrade or destroy electronics.

The design response to these two categories overlaps significantly, but they are not identical problems. Hardening against unintentional EMI involves careful layout, shielding, filtering, and grounding. Hardening against intentional electromagnetic attack requires a different order of magnitude of robustness and, in many cases, changes to the fundamental architecture of the system rather than its physical construction. This distinction matters because it affects both the testing regime and the procurement specification.

In the context of this series, readers who have worked through the post on LoRa for Defence Sectors will recall the discussion of LoRa’s spread-spectrum modulation and its inherent resistance to narrowband interference. That resilience is one manifestation of EMI hardening at the physical layer. The post on MAVLink integration in defence UAVs raised the parallel challenge of maintaining reliable datalink integrity in contested RF environments. EMC design is the engineering discipline that underpins both of those specific topics.

Why the Grounding Strategy is a misunderstood element of defence EMC design

Grounding is the area where more defence EMC programmes encounter avoidable problems than perhaps any other. The instinct of many engineers is to regard ground as a passive reference plane, a convenient zero-volt rail to which everything else is referred. In high-frequency or mixed-signal hardware operating in an RF-rich environment, this model is not simply incomplete; it is actively misleading.

At frequencies above a few hundred kilohertz, current follows the path of least impedance, not least resistance. A poor ground return path that looks entirely acceptable at DC will behave as an antenna at 100 MHz. Defence electronics routinely operate in or near frequency bands where this becomes critical: C-band radar, L-band satellite communications, and the HF to UHF spectrum used by tactical radio networks all create electromagnetic environments where grounding strategy directly affects both emissions performance and immunity.

For digital subsystems operating at clock speeds typical of modern processing hardware, a dedicated continuous ground plane beneath the routing layer is the baseline expectation. Splits in the ground plane, which are sometimes used to achieve galvanic isolation between analogue and digital domains, must be managed with deliberate awareness of the return path they create at high frequencies. Where analogue-to-digital conversion is involved, as is the case with the tactical sensor hardware covered in the post on tactical sensor power design, the interaction between power supply noise, ground structure, and ADC reference voltage demands careful attention at the layout stage rather than at prototype bring-up.

Shielding effectiveness in military-grade enclosures

Electromagnetic shielding in defence electronics serves a dual function: it attenuates emissions leaving the enclosure and reduces the field strength of external interference reaching the internal circuitry. The effectiveness of a shield is expressed in decibels and is frequency-dependent. A continuous steel enclosure with no apertures can achieve extremely high shielding effectiveness across a broad frequency range. The moment apertures are introduced, whether for ventilation, connectors, display windows, or controls, the shielding effectiveness of the assembly degrades.

This is not a counsel against apertures; practical hardware requires them. It is a statement that each aperture must be treated as a design decision with EMC consequences. A ventilation slot array that performs adequately as a heat management solution may simultaneously act as a resonant structure at a frequency directly relevant to the threat environment. The design solution typically involves keeping slot lengths shorter than one-twentieth of the wavelength at the highest frequency of concern, utilising wire mesh or honeycomb vent panels where feasible, and applying conductive gaskets to all mating faces to maintain enclosure continuity.

Connector penetrations are a particularly important category. Unfiltered signal or power cables entering an otherwise shielded enclosure create a direct path for conducted interference. Filtered connector assemblies, which integrate low-pass or band-pass filter networks directly at the shell or bulkhead, are the standard solution for high-integrity defence enclosures. The selection of filter characteristics must account for the signal bandwidth requirements of the interface: an overly aggressive low-pass filter on a data line will impair signal integrity in ways that are sometimes more damaging than the interference it was designed to exclude.

PCB layout practices for Defence EMC compliance

The printed circuit board (PCB) is where EMC performance is won or lost. The decisions made during PCB layout determine whether the hardware will pass DEF STAN 59-411 testing or require expensive board respins. Experienced defence electronics engineers understand that EMC is not a feature that can be added to a design after layout is complete; it is a consequence of the layout itself.

The routing of high-speed signal traces is among the most consequential of these decisions. A high-speed trace carrying a clock or data signal with fast edge rates is a transmitting antenna. Its return path, which flows in the ground plane immediately beneath it if the layout is correct, is also part of that antenna structure. Deviations in the return path, caused by gaps in the ground plane, vias that interrupt the return current, or routing that crosses plane splits, produce radiation that is often difficult to suppress after the fact.

Decoupling capacitor placement is a closely related concern. The function of a decoupling capacitor is to supply instantaneous current to a switching device from a local reservoir, preventing that current from being drawn through the inductance of the power distribution network and radiating in the process. A decoupling capacitor that is placed two centimetres from the device it serves, with its return path routed through multiple vias, provides a fraction of the benefit of the same capacitor placed immediately adjacent to the power pin with a direct return to the nearest ground via. This is understood in principle by most PCB designers. In practice, however, placement is often compromised by other routing constraints, and the EMC consequences are only discovered at test.

The power distribution design considerations discussed in the tactical sensor power design post are directly relevant here. Efficient power architecture reduces switching noise at the source; good PCB layout determines whether that noise couples into the signal domain or the radiation environment.

Filtering strategies for power and signal lines

EMI filtering on power input lines is a requirement rather than an option for defence-grade hardware. Military power environments, particularly vehicle 24V DC and aircraft 28V DC buses, carry conducted noise signatures that significantly exceed what commercial power supplies are designed to tolerate. Transients from load switching, alternator ripple, generator harmonics, and the conducted emissions of adjacent equipment on the same bus all present as threats to the power input of the equipment under design.

As previously mentioned, the defence standard for power quality on UK military platforms is DEF STAN 61-5, which defines the characteristics of the power supply environment that equipment must tolerate. The design response typically involves a multi-stage input filter combining common-mode inductors, differential-mode capacitors, and transient voltage suppression devices rated to the appropriate threat level. The filter design must be validated not just for attenuation characteristics but for stability: an underdamped filter network connected to the output impedance of a military power supply can produce resonances that amplify rather than attenuate certain interference frequencies.

Signal line filtering requires a different approach. Where power line filters are designed to pass DC and low-frequency content while blocking high-frequency noise, signal line filters must be tailored to the specific bandwidth of the signal they carry. A blanket ferrite bead on every signal line is not a defence EMC strategy; it is an approximation that may introduce signal integrity problems while providing inconsistent protection. The correct approach is to characterise the signal bandwidth, identify the interference frequencies of concern, and select filter components with the insertion loss profile that addresses the threat without degrading the signal.

Engineers working on secure OTA update systems for defence IoT hardware, a topic addressed in the post on secure OTA for defence systems, will recognise the relevance of this to RF interfaces. The antenna feed network is itself a filtering structure, and its design has direct consequences for both the conducted emissions signature of the radio subsystem and its susceptibility to external interference.

EMC testing regimes for UK Defence Procurement

DEF STAN 59-411 defines a comprehensive suite of tests across four parts: Part 1 covers management requirements and the EMC programme, Part 2 specifies the technical requirements and measurements, Part 3 addresses installation requirements, and Part 4 provides guidance on the application of the standard. Understanding the structure of the standard is important for programme planning because the testing regime it mandates is substantially more demanding than the commercial CE marking tests with which engineers from non-defence backgrounds may be more familiar.

The emissions tests cover both conducted and radiated emissions across frequency ranges extending from below 10 kHz to above 18 GHz in some equipment categories. The immunity tests include radiated susceptibility at field strengths representative of the operating environment, conducted susceptibility on power and signal lines, and transient tests representing the switching events and electrostatic discharge threats specific to military service. For certain platform types, additional tests addressing lightning indirect effects, electrostatic discharge from personnel, and high-power electromagnetic (HPEM) environments are applicable.

Pre-compliance testing during development is strongly recommended. Waiting until the hardware is complete to discover that emissions exceed the applicable limit by 20 dB is an expensive way to learn that the layout needed a ground plane. Iterative EMC testing using a near-field probe and a spectrum analyser during the prototype phase can identify the dominant emission sources while the hardware is still in a state where corrections are feasible. This approach requires more engineering time during development but consistently reduces total programme cost by avoiding late-stage design changes.

Electronic warfare hardening: Beyond standard compliance

Passing DEF STAN 59-411 is necessary but not always sufficient. For equipment intended for deployment in contested electromagnetic environments, particularly where the threat from directed electronic warfare is credible, the design must go further than the standard requires. This involves a structured assessment of the threat environment, expressed in terms of the frequencies, field strengths, and pulse characteristics of the known or anticipated EW threat, and a design response calibrated to that assessment.

At the circuit level, EW hardening typically involves a combination of measures: overvoltage protection on all external interfaces, including RF ports; receiver front-end designs that limit the energy that can be injected into sensitive active components; use of optocoupled or transformer-isolated interfaces where conducted injection is a threat path; and the selection of components with demonstrated robustness under high-field exposure. For software-defined radio architectures, which are increasingly common in defence communications equipment, the firmware layer also plays a role: the ability to detect and respond to jamming or spoofing at the signal processing level is part of the system’s overall electromagnetic resilience.

The discussion of secure OTA update mechanisms in this series is relevant here from a different angle. Electronic warfare increasingly targets the software layer of defence systems as much as the hardware. A system that is electromagnetically hardened at the circuit level but vulnerable to firmware injection through an unsecured update interface has not addressed its full threat surface. The intersection of EMC, cybersecurity, and system architecture is where the most demanding defence design challenges currently sit.

Final Thoughts: Integrating EMC Strategy into the Defence Development Programme

The most effective defence EMC programmes treat electromagnetic compatibility as a system-level discipline that runs in parallel with the hardware and firmware development stream, not as a series of tests to be passed at programme milestones. This means establishing an EMC programme plan at programme initiation, identifying the applicable standard set and test requirements before the design baseline is frozen, and assigning EMC accountability within the engineering team rather than delegating it to the test laboratory at the end of the project.

In practice, this involves a series of structured reviews. The EMC design review, conducted before PCB layout commences, should examine the proposed grounding strategy, layer stack, shielding approach, and filter design against the requirements of the applicable standard. The pre-compliance test campaign, conducted on the first prototype, identifies the dominant non-conformances and informs the corrective design changes. The formal compliance test, conducted on a production-representative unit, provides the evidence base for the acceptance documentation.

For programme managers, this structured approach provides the visibility needed to manage schedule and cost risk. EMC redesign is one of the most common sources of late-stage programme cost growth in defence electronics development. A programme that has invested in EMC design review and pre-compliance testing is substantially less likely to encounter the scenario where a hardware design must be fundamentally revised weeks before acceptance testing. The investment in EMC engineering during development is, in almost every case, less than the cost of the redesign it prevents.

Ignitec applies this integrated approach across its defence electronics design work, from the initial schematic review through to pre-compliance testing and acceptance support. Whether the project involves tactical sensor hardware, UAV datalink electronics, or the power management systems discussed elsewhere in this series, the electromagnetic environment is treated as a design parameter from day one.

If you are developing defence electronics hardware and want to discuss what a structured EMC programme looks like for your specific platform and UK MOD procurement pathway, get in touch with an expert on our team.